1. Field
Exemplary embodiments of the present invention relate to a memory capable of simplifying an interconnection pattern of a metal line and minimizing an area of the metal line.
2. Description of the Related Art
A memory is classified into a volatile memory and a non-volatile memory according to data retention when power is off. The volatile memory is a memory in which data is lost when power is off. Examples of the volatile memory include a DRAM and a SRAM. The non-volatile memory is a memory in which stored data is retained although power is off. Example of the non-volatile memory includes a flash memory.
FIG. 1 is a circuit diagram illustrating one set of even/odd bit lines BLE and BLO, a bit line selection unit 110, and a page buffer 120 that correspond to one another in a memory in accordance with prior art.
As illustrated in FIG. 1, a page buffer 120 corresponds to two bit lines, that is, the even bit line BLE and the odd bit line BLO, and the bit line selection unit 110 is connected between the page buffer 120 and the two bit lines BLE and BLO that correspond to each other, and electrically connects a selected one of the two bit lines BLE and BLO to the page buffer 120 in response to bit line selection signals SEL_BLE and SEL_BLO.
The bit line selection unit 110 includes an even selection transistor N1, which is turned on/off in response to the even bit line selection signal SEL_BLE, and an odd selection transistor N2, which is turned on/off in response to the odd bit line selection signal SEL_BLO. The even selection transistor N1 is turned on when the even bit line selection signal SEL_BLE is activated, and electrically connects the even bit line BLE to the page buffer 120. The odd selection transistor N2 is turned on when the odd bit line selection signal SEL_BLO is activated, and electrically connects the odd bit line BLO to the page buffer 120.
The page buffer 120 performs an operation for detecting a voltage of an electrically connected bit line or driving the bit line by a specific voltage when performing a program operation, a verification operation, a read operation, or an erase operation of a plurality of memory cells (not illustrated in FIG. 1) included in the memory.
Meanwhile, in the memory, a plurality of bit line selection units and a plurality of page buffers are arranged in an array form. That is, the plurality of bit line selection units are arranged in an array form in a bit line selection area, and the plurality of page buffers are arranged in an array form in a page buffer area. Among the plurality of bit line selection units and the plurality of page buffers, a bit line selection unit and a page buffer corresponding to each other are connected to each other through a connection metal line formed across the bit line selection area and the page buffer area.
In the page buffer area, a plurality of global pads are formed to apply a control signal to the plurality of page buffers, and in the bit line selection unit, bit line pads are formed to connect bit lines to each other. Since the connection metal line connects the page buffer to the bit line selection unit while avoiding the plurality of global pads and the bit line pads, patterns of a plurality of connection metal lines become complicated due to the positions of the plurality of global pads and the plurality of bit line pads. Particularly, the complication of the patterns of the plurality of connection metal lines becomes even more complex in an area, where the page buffer area and the bit line selection area are adjacent to each other.